1. Field of the Invention
The present invention relates to insulated gate semiconductor devices and manufacturing methods thereof and, particularly to the device structure with a low ON voltage of an insulated gate bipolar transistor having a trench MOS gate and a manufacturing method thereof.
2. Description of the Background Art
FIG. 26 is a cross-sectional view of a conventional insulated gate semiconductor device, and a description is made on an insulated gate bipolar transistor with the trench gate structure (referred to as an IGBT, hereinafter, and an IGBT with the trench gate structure is referred to as a U-type IGBT) as an example.
Recently, the IGBTs are used in the voltage resonance circuits, which are high frequency inverters for energy conservation, miniaturization, and weight reduction of household electric appliances, and used in intelligent power modules for performing variable speed control of three-phase motors in the fields of the general purpose inverters, the AC servo, and the air conditioners, etc., and they are now in general use. In the IGBTs, which are key devices thereof, devices with good switching characteristic, low saturation voltage and large SOA (Safe Operating Area) are demanded while the switching characteristic, the saturation voltage and the SOA are in the trade-off relation.
In FIG. 26, the reference numeral 1 denotes a P.sup.+ collector layer, the reference numeral 2 denotes an N.sup.- layer, the reference numeral 3 denotes a P base layer, the reference numeral 4 denotes an N.sup.+ emitter layer, the reference numeral 5 denotes a trench, the reference numeral 6 denotes a gate insulating film, the reference numeral 7 denotes a gate electrode, the reference numeral 8 denotes an interlayer insulating film, the reference numeral 9 denotes an N.sup.+ buffer layer, the reference numeral 10 denotes an emitter electrode, the reference numeral 11 denotes a collector electrode, and the reference numeral 12 denotes a channel region.
Next, operation of the IGBT will be described.
When a certain collector voltage V.sub.CE is applied between the emitter electrode 10 and the collector electrode 11 and a certain gate voltage V.sub.GE is applied between the emitter electrode 10 and the gate electrode 7, that is, when the gate is turned on, the channel region 12 is inverted into the N-type and a channel is formed. Electrons are injected from the emitter electrode 10 through the channel into the N.sup.- layer 2. The injected electrons establish forward bias between the P.sup.+ collector layer 1 and the N.sup.- layer 2 and holes are injected from the collector electrode 11 via the P.sup.+ collector layer 1 and the N.sup.+ buffer layer 9 into the N.sup.- layer 2. As a result, resistance of the N.sup.- layer 2 decreases because of the conductivity modulation and the current capacity of the IGBT increases. The voltage drop between collector-emitter of the IGBT at this time is the ON voltage (V.sub.CE(SAT)).
Next, when turning the IGBT from an ON state to an OFF state, the gate voltage V.sub.GE applied between the emitter electrode 10 and the gate electrode 7 is brought to 0 V or the backward bias, that is, the gate is turned off, and then the channel region 12 inverted into the N-type returns to the P-type and the injection of electrons from the emitter electrode 10 is stopped. Subsequently, the electrons and holes accumulated in the N.sup.- layer 2 go through to the collector electrode 11 and the emitter electrode 10, respectively, or they are recombined and disappear.
Generally, the ON voltage of the IGBT is mostly determined by substantial resistance of the N.sup.- layer 2 required to hold the breakdown voltage. Factors of the substantial resistance include the electron supplying capability of the MOSFET forming the IGBT. In the structure of the U-type IGBT in which a narrow and deep trench is formed in the surface of a chip and a MOSFET is formed on the sidewall thereof, the electron supplying capability of the MOSFET can be increased by reducing the unit cell interval as much as possible.
FIG. 27 is a circuit diagram showing an equivalent circuit of the IGBT.
In FIG. 27, the reference numeral 15 is a bipolar transistor, and the reference numeral 16 is a MOSFET.
Generally, the IGBT is represented by the equivalent circuit shown in FIG. 27. Since h.sub.fe of the bipolar transistor 15 formed of the P.sup.+ collector layer 1, the N layer of a combination of the N.sup.+ buffer layer 9 and the N.sup.- layer 2, and the P base layer of the IGBT is small, however, the IGBT can be considered a combination of the MOSFET and the diode 17.
FIG. 28 is a circuit diagram showing an equivalent circuit of the IGBT when h.sub.fe of the bipolar transistor 15 is assumed small.
In FIG. 28, the reference numeral 17 is a diode and the reference numeral 18 is a MOSFET.
FIG. 29 is a graph showing the carrier concentration distribution of an N.sup.- layer in an ON state of a PIN diode.
As the MOSFET 18 can be regarded as a mere switching element in FIG. 28, the carrier concentration distribution of the N.sup.- layer of the PIN diode 17 of the IGBT should be something like the carrier concentration distribution of the N.sup.- layer of the PIN diode as shown in FIG. 29, but it is not.
FIG. 30 is a graph showing the carrier concentration distribution of the N.sup.- layer 2 in an ON state in a conventional IGBT.
While the carrier concentration of the N.sup.- layer in the ON state of the PIN diode is uniform between the end of the N.sup.- layer on the anode side and the end on the cathode side as shown in FIG. 29, the carrier concentration of the N.sup.- layer 2 in the ON state in the conventional IGBT gradually decreases from the end of the N.sup.- layer 2 on the collector side to the end on the emitter side, as shown in FIG. 30. Accordingly, the ON voltage of the conventional IGBT is higher than that of the diode.
Especially, in the IGBT with a high breakdown voltage, the breakdown voltage is secured by increasing the thickness of the N.sup.- layer 2. The gradient of the decrease of the carrier concentration of the N.sup.- layer 2 from the end on the collector side toward the end on the emitter side is not affected by the thickness of the N.sup.- layer 2 if the carrier life time is the same, so that the difference in the carrier concentration between the end on the collector side and the end on the emitter side increases as the N.sup.- layer 2 becomes thicker, and the difference in the ON voltage from the diode increases as the IGBT has a higher breakdown voltage.
Various devices are considered for the purpose of eliminating such a difference between the ON voltage of the IGBT and the ON voltage of the diode, which is considered limiting value of the ON voltage of the IGBT. They include the MCT (MOS CONTROLLED THYRISTOR) and the IEGT (INJECTION ENHANCED GATE BIPOLAR TRANSISTOR).
FIG. 31 is a cross-sectional view showing the structure of the MCT.
In FIG. 31, the reference numeral 21 denotes an N.sup.+ cathode region, the reference numeral 22 denotes an N region, the reference numeral 23 denotes a P.sup.+ region, the reference numeral 24 denotes a channel region in gate on, and the reference numeral 25 denotes a channel region in gate off, or an OFF channel region. Other reference characters are the same as those in FIG. 26.
It is known that the carrier concentration distribution of the N.sup.- layer 2 in the ON state in the MCT generally takes the distribution similar to that of a diode. Accordingly, the ON voltage is lower in the MCT than in the IGBT with the conventional structure.
However, when off, the P-channel MOS formed of the P base layer 3, the N region 22 and the P.sup.+ region 23 forms a channel by the inversion of the OFF channel region 25, through which channel holes flow. Hence, there is a problem that the current value capable of being turned off can not be large, considering that the resistance of the OFF channel region 25 is generally high. There is also a problem that the processes are complicated and the devices are expensive because an N-channel MOS for ON and a P-channel MOS for OFF must be formed in the triple diffusion in the surface.
Examples of the IEGT include one disclosed in Japanese Patent Laying-Open No. 5-243561.
For example, in the IEGT shown in FIG. 101 of Japanese Patent Laying-Open No. 5-243561, the N emitter regions and the P base regions of some cells in the U-type IGBT are coated with insulating layers, and the contact between the N emitter regions and the P base regions, and the emitter electrode is eliminated.
Operation of the IEGT is basically the same as that of the U-type IGBT, but, since the cells are formed in which contact between the N emitter region and the P base region, and the emitter electrode is not formed, the hole current going through to the P base region in the ON state is restricted, holes are accumulated in the N-type base layer surface, and the carrier concentration distribution of the N-type base layer results in the same one as that of a diode, and the ON voltage of the IEGT becomes lower than the U-type IGBT.
It operates basically in the same way as the U-type IGBT also in the OFF state, but a less number of cells operate as compared with the U-type IGBT when holes accumulated in the N-type base layer go through to the emitter electrode, and the holes go through a less number of cells.
The movement of holes at this time becomes a base current of a parasitic bipolar transistor formed of the N-type base layer, the P base region and the emitter region, and when it exceeds the built-in potential (generally 0.6 V), the parasitic bipolar transistor turns on. Accordingly, in the IEGT in which part of cells of the U-type IGBT are taken away, a current value capable of being turned off may have to be set smaller than in the common U-type IGBT so that the parasitic transistor will not turn on.